B&B Electronics RS-232 to Ethernet Converter ES1A Especificaciones Pagina 62
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- Tabla de contenidos
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Valorado. / 5. Basado en revisión del cliente
Si3216
62 Rev. 1.0
Not Recommended
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Reset settings = 0000_1000
Register 10. Two-Wire Impedance Synthesis Control
BitD7D6D5D4D3D2D1D0
Name
CLC[1:0] TISE TISS[2:0]
Type R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:4 CLC[1:0]
Line Capacitance Compensation.
00 = Off
01 = 4.7 nF
10 = 10 nF
11 = Reserved
3TISE
Two-Wire Impedance Synthesis Enable.
0 = Two-wire impedance synthesis disabled.
1 = Two-wire impedance synthesis enabled.
2:0 TISS[2:0]
Two-Wire Impedance Synthesis Selection.
000 = 600
001 = 900
010 = Japan (600 + 1 µF); requires external resistor R
ZREF
=12k and C3, C4 = 100 nF.
011 = 900
+ 2.16 µF; requires external resistor R
ZREF
=18k and C3, C4 = 220 nF.
100 = CTR21 (270
+ 750 || 150 nF).
101 = Australia/New Zealand #1 (220
+ 820 || 120 nF).
110 = Slovakia/Slovenia/South Africa (220
+ 820 || 115 nF).
111 = China (200
+ 680 || 100 nF).
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.0 2
- TABLE OF CONTENTS 3
- 1. Electrical Specifications 4
- 8 Rev. 1.0 8
- Rev. 1.0 11 11
- 12 Rev. 1.0 12
- Rev. 1.0 13 13
- 14 Rev. 1.0 14
- Parameter 17
- Symbol Test Condition 17
- Max Unit 17
- Figure 9. SPI Timing Diagram 19
- Si3216(M) 20
- Rev. 1.0 21 21
- Rev. 1.0 23 23
- Component (s) Value Supplier 25
- , 1/10 W, ±5% 25
- 26 Rev. 1.0 26
- 2. Functional Description 27
- 2.1.2. Linefeed Architecture 28
- . The ProSLIC can 28
- Rev. 1.0 29 29
- Parameter Description/ 31
- Resolution Register 31
- Location* 31
- Closure Detection 32
- Switching 33
- 34 Rev. 1.0 34
- Figure 19. V 35
- in the Forward Active State 35
- 2.3. Tone Generation 36
- Tone Generator 1 38
- Tone Generator 2 38
- 2.4. Ringing Generation 39
- 2.4.2. Sinusoidal Ringing 40
- 2.4.3. Trapezoidal Ringing 40
- Location 40
- T=1/freq 41
- Figure 23. Ring Trip Detector 42
- 2.5. Audio Path 43
- 44 Rev. 1.0 44
- Rev. 1.0 45 45
- 2.7. Clock Generation 46
- 2.8. Interrupt Logic 46
- Rev. 1.0 47 47
- 48 Rev. 1.0 48
- 2.10. PCM Interface 49
- 50 Rev. 1.0 50
- Rev. 1.0 51 51
- 3. Control Registers 52
- Rev. 1.0 53 53
- 54 Rev. 1.0 54
- Rev. 1.0 55 55
- CALM1 CALM2 CALDAC CALADC 55
- 56 Rev. 1.0 56
- Rev. 1.0 57 57
- 58 Rev. 1.0 58
- Rev. 1.0 59 59
- 60 Rev. 1.0 60
- Rev. 1.0 61 61
- 62 Rev. 1.0 62
- Rev. 1.0 63 63
- 64 Rev. 1.0 64
- Rev. 1.0 65 65
- 66 Rev. 1.0 66
- Rev. 1.0 67 67
- 68 Rev. 1.0 68
- Rev. 1.0 69 69
- 70 Rev. 1.0 70
- Rev. 1.0 71 71
- 72 Rev. 1.0 72
- Rev. 1.0 73 73
- 74 Rev. 1.0 74
- Rev. 1.0 75 75
- 76 Rev. 1.0 76
- Rev. 1.0 77 77
- 78 Rev. 1.0 78
- Rev. 1.0 79 79
- 80 Rev. 1.0 80
- Rev. 1.0 81 81
- 82 Rev. 1.0 82
- Rev. 1.0 83 83
- 84 Rev. 1.0 84
- Rev. 1.0 85 85
- 86 Rev. 1.0 86
- Rev. 1.0 87 87
- 88 Rev. 1.0 88
- Rev. 1.0 89 89
- 90 Rev. 1.0 90
- Rev. 1.0 91 91
- 92 Rev. 1.0 92
- Rev. 1.0 93 93
- 94 Rev. 1.0 94
- Rev. 1.0 95 95
- 96 Rev. 1.0 96
- Rev. 1.0 97 97
- 98 Rev. 1.0 98
- Rev. 1.0 99 99
- 100 Rev. 1.0 100
- Rev. 1.0 101 101
- 102 Rev. 1.0 102
- Rev. 1.0 103 103
- 4. Indirect Registers 104
- Rev. 1.0 105 105
- 106 Rev. 1.0 106
- Rev. 1.0 107 107
- 108 Rev. 1.0 108
- Rev. 1.0 109 109
- 5. Pin Descriptions: Si3216 110
- Rev. 1.0 111 111
- 112 Rev. 1.0 112
- 6. Pin Descriptions: Si3201 113
- 7. Ordering Guides 114
- Rev. 1.0 115 115
- 116 Rev. 1.0 116
- Rev. 1.0 117 117
- 118 Rev. 1.0 118
- Rev. 1.0 119 119
- DOCUMENT CHANGE LIST 120
- Rev. 1.0 121 121
- CONTACT INFORMATION 122
- Mouser Electronics 123
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