
Si3216
18 Rev. 1.0
Not Recommended
f
o
r N
e
w
D
e
si
g
n
s
Table 10. Switching Characteristics—General Inputs
V
DDA
=V
DDA
= 3.13 to 5.25 V, T
A
= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C
L
=20pF)
Parameter Symbol Min Typ Max Unit
Rise Time, RESET t
r
——20ns
RESET
Pulse Width t
rl
100 — — ns
Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
V
IH
=V
D
– 0.4 V, V
IL
= 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
Table 11. Switching Characteristics—SPI
V
DDA
=V
DDA
= 3.13 to 5.25 V, T
A
= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C
L
=20pF
Parameter
Symbol
Test
Conditions
Min Typ Max Unit
Cycle Time SCLK t
c
0.062 — — s
Rise Time, SCLK t
r
— — 25 ns
Fall Time, SCLK t
f
— — 25 ns
Delay Time, SCLK Fall to SDO Active t
d1
— — 20 ns
Delay Time, SCLK Fall to SDO
Transition
t
d2
— — 20 ns
Delay Time, CS
Rise to SDO Tri-state t
d3
— — 20 ns
Setup Time, CS
to SCLK Fall t
su1
25 — — ns
Hold Time, CS
to SCLK Rise t
h1
20 — — ns
Setup Time, SDI to SCLK Rise t
su2
25 — — ns
Hold Time, SDI to SCLK Rise t
h2
20 — — ns
Delay Time between Chip Selects
(Continuous SCLK)
t
cs
440 — — ns
Delay Time between Chip Selects
(Non-continuous SCLK)
t
cs
220 — — ns
SDI to SDITHRU Propagation Delay t
d4
— 4 10 ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are V
IH
=V
DDD
–0.4 V, V
IL
=0.4V
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