B&B Electronics RS-232 to Ethernet Converter ES1A Especificaciones Pagina 20
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Valorado. / 5. Basado en revisión del cliente
Si3216
20 Rev. 1.0
Not Recommended
f
o
r N
e
w
D
e
si
g
n
s
Figure 10. PCM Highway Interface Timing Diagram
Figure 11. Si3216(M) Application Circuit Using Si3201
PCLK
DRX
FSYNC
DTX
t
d1
t
d2
t
su2
t
h2
t
d3
t
r
t
c
t
su1
t
h1
t
f
Si3201
4
Si3216(M)
R15
243
C2
10 F
C1
10 F
R14
40.2k
C5
22nF
C6
22nF
ITIPN
IRINGN
ITIPP
IRINGP
STIPE
SRINGE
ITIPN
IRINGN
ITIPP
IRINGP
STIPE
SRINGE
TIP
RING
GND
VBAT
TIP
RING
VDDD
VDDA1
GNDD
GNDA
IREF
CAPP
CAPM
IGMP
IGMN
QGND
SCLK
SDI
SDO
CS
FSYNC
PCLK
DRX
DTX
SPI Bus
PCM
Bus
VDDA2
INT
RESET
R5
200k
R28
1
R21
15
VDD
Protection
Circuit
C24
0.1 F
C19
4.7 F
R6
4.02k
R7
4.02k
VBATH
SVBAT
29
25
28
26
17
19
18
1
3
4
5
15
13
16
14
11
10
8
7
31
23
10
27
30
TEST
32
38
37
36
1
6
3
4
5
2
7
24
22
11
12
14
13
Q9
2N2222
C26
0.1 F
R29
1
VCC
VCC
VCC
SDCL
SDCH
DC-DC Converter
Circuit
DCDRV
DCFF
VDC
VBAT
VDC
SDCL
SDCH
DCDRV
DCFF
STIPDC
STIPAC
R26
2
40.2k
GND
R32
2
10k
VCC
Note 2
Note 1
9
8
34
33
C18
4.7 F
R1
200k
15
20
C3
220 nF
R8
4.7K
R3
200k
21
16
C4
220 nF
R9
4.7K
SRINGAC
SRINGDC
Notes:
1. Values and configurations for these
components can be derived from Table 18
or from App Note 45.
2. Only one component per system needed.
3. All circuit ground should have a single-point
connection to the ground plane.
4. Si3201 bottom-side exposed pad should be
electrically and thermally connected to bulk
ground plane.
R2
196k
R4
196k
VDDA1
C30
10 F
VDDA2
VDDD
C16
0.1 F
C15
0.1 F
C17
0.1 F
10 F
10 V
C31
47 H
L2
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.0 2
- TABLE OF CONTENTS 3
- 1. Electrical Specifications 4
- 8 Rev. 1.0 8
- Rev. 1.0 11 11
- 12 Rev. 1.0 12
- Rev. 1.0 13 13
- 14 Rev. 1.0 14
- Parameter 17
- Symbol Test Condition 17
- Max Unit 17
- Figure 9. SPI Timing Diagram 19
- Si3216(M) 20
- Rev. 1.0 21 21
- Rev. 1.0 23 23
- Component (s) Value Supplier 25
- , 1/10 W, ±5% 25
- 26 Rev. 1.0 26
- 2. Functional Description 27
- 2.1.2. Linefeed Architecture 28
- . The ProSLIC can 28
- Rev. 1.0 29 29
- Parameter Description/ 31
- Resolution Register 31
- Location* 31
- Closure Detection 32
- Switching 33
- 34 Rev. 1.0 34
- Figure 19. V 35
- in the Forward Active State 35
- 2.3. Tone Generation 36
- Tone Generator 1 38
- Tone Generator 2 38
- 2.4. Ringing Generation 39
- 2.4.2. Sinusoidal Ringing 40
- 2.4.3. Trapezoidal Ringing 40
- Location 40
- T=1/freq 41
- Figure 23. Ring Trip Detector 42
- 2.5. Audio Path 43
- 44 Rev. 1.0 44
- Rev. 1.0 45 45
- 2.7. Clock Generation 46
- 2.8. Interrupt Logic 46
- Rev. 1.0 47 47
- 48 Rev. 1.0 48
- 2.10. PCM Interface 49
- 50 Rev. 1.0 50
- Rev. 1.0 51 51
- 3. Control Registers 52
- Rev. 1.0 53 53
- 54 Rev. 1.0 54
- Rev. 1.0 55 55
- CALM1 CALM2 CALDAC CALADC 55
- 56 Rev. 1.0 56
- Rev. 1.0 57 57
- 58 Rev. 1.0 58
- Rev. 1.0 59 59
- 60 Rev. 1.0 60
- Rev. 1.0 61 61
- 62 Rev. 1.0 62
- Rev. 1.0 63 63
- 64 Rev. 1.0 64
- Rev. 1.0 65 65
- 66 Rev. 1.0 66
- Rev. 1.0 67 67
- 68 Rev. 1.0 68
- Rev. 1.0 69 69
- 70 Rev. 1.0 70
- Rev. 1.0 71 71
- 72 Rev. 1.0 72
- Rev. 1.0 73 73
- 74 Rev. 1.0 74
- Rev. 1.0 75 75
- 76 Rev. 1.0 76
- Rev. 1.0 77 77
- 78 Rev. 1.0 78
- Rev. 1.0 79 79
- 80 Rev. 1.0 80
- Rev. 1.0 81 81
- 82 Rev. 1.0 82
- Rev. 1.0 83 83
- 84 Rev. 1.0 84
- Rev. 1.0 85 85
- 86 Rev. 1.0 86
- Rev. 1.0 87 87
- 88 Rev. 1.0 88
- Rev. 1.0 89 89
- 90 Rev. 1.0 90
- Rev. 1.0 91 91
- 92 Rev. 1.0 92
- Rev. 1.0 93 93
- 94 Rev. 1.0 94
- Rev. 1.0 95 95
- 96 Rev. 1.0 96
- Rev. 1.0 97 97
- 98 Rev. 1.0 98
- Rev. 1.0 99 99
- 100 Rev. 1.0 100
- Rev. 1.0 101 101
- 102 Rev. 1.0 102
- Rev. 1.0 103 103
- 4. Indirect Registers 104
- Rev. 1.0 105 105
- 106 Rev. 1.0 106
- Rev. 1.0 107 107
- 108 Rev. 1.0 108
- Rev. 1.0 109 109
- 5. Pin Descriptions: Si3216 110
- Rev. 1.0 111 111
- 112 Rev. 1.0 112
- 6. Pin Descriptions: Si3201 113
- 7. Ordering Guides 114
- Rev. 1.0 115 115
- 116 Rev. 1.0 116
- Rev. 1.0 117 117
- 118 Rev. 1.0 118
- Rev. 1.0 119 119
- DOCUMENT CHANGE LIST 120
- Rev. 1.0 121 121
- CONTACT INFORMATION 122
- Mouser Electronics 123
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