
Si3216
Rev. 1.0 19
Not Recommended
f
o
r N
e
w
D
e
si
g
n
s
Figure 9. SPI Timing Diagram
Table 12. Switching Characteristics—PCM Highway Serial Interface
V
D
= 3.13 to 5.25 V, T
A
= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C
L
=20pF
Parameter
Symbol
Test
Conditions
Min
1
Typ
1
Max
1
Units
PCLK Frequency 1/t
c
—
—
—
—
—
—
—
—
0.256
0.512
0.768
1.024
1.536
2.048
4.096
8.192
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PCLK Duty Cycle Tolerance t
dty
40 50 60 %
PCLK Period Jitter Tolerance t
jitter
–120 — 120 ns
Rise Time, PCLK t
r
——25ns
Fall Time, PCLK t
f
——25ns
Delay Time, PCLK Rise to DTX Active t
d1
——20ns
Delay Time, PCLK Rise to DTX
Transition
t
d2
——20ns
Delay Time, PCLK Rise to DTX Tri-state
2
t
d3
——20ns
Setup Time, FSYNC to PCLK Fall t
su1
25 — — ns
Hold Time, FSYNC to PCLK Fall t
h1
20 — — ns
Setup Time, DRX to PCLK Fall t
su2
25 — — ns
Hold Time, DRX to PCLK Fall t
h2
20 — — ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
IH –
V
I/O –
0.4 V, V
IL
=0.4V.
2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
SCLK
CS
SDI
t
h1
t
d3
SDO
t
d1
t
d2
t
su1
t
r
t
r
t
c
t
su2
t
h2
t
cs
t
thru
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