
Si3216
Rev. 1.0 31
Not Recommended
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Table 24. Associated Power Monitoring and Power Fault Registers
Parameter Description/
Range
Resolution Register
Bits
Location*
Power Monitor Pointer
0 to 5 points to Q1
to Q6, respectively
N/A
PWRMP[2:0] Direct Register 76
Line Power Monitor Output
0 to 7.8 W for Q1,
Q2, Q5, Q6
0 to 0.9 W for Q3,
Q4
30.4 mW
3.62 mW
PWROM[7:0] Direct Register 77
Power Alarm Threshold, Q1 & Q2 0 to 7.8 W 30.4 mW PPT12[7:0] Indirect Register 19
Power Alarm Threshold, Q3 & Q4 0 to 0.9 W 3.62 mW PPT34[7:0] Indirect Register 20
Power Alarm Threshold, Q5 & Q6 0 to 7.8 W 30.4 mW PPT56[7:0] Indirect Register 21
Thermal LPF Pole, Q1 & Q2
See equation in “2.1.5. Power
Monitoring and Line Fault Detec-
tion”
NQ12[7:0] Indirect Register 24
Thermal LPF Pole, Q3 & Q4
See equation in “2.1.5. Power
Monitoring and Line Fault Detec-
tion”
NQ34[7:0] Indirect Register 25
Thermal LPF Pole, Q5 & Q6
See equation in “2.1.5. Power
Monitoring and Line Fault Detec-
tion”
NQ56[7:0] Indirect Register 26
Power Alarm Interrupt Pending
Bits 2 to 7 corre-
spond to Q1 to Q6,
respectively
N/A
QnAP[n+1],
where n = 1 to 6
Direct Register 19
Power Alarm Interrupt Enable
Bits 2 to 7 corre-
spond to Q1 to Q6,
respectively
N/A
QnAE[n+1],
where n = 1 to 6
Direct Register 22
Power Alarm
Automatic/Manual Detect
0 = manual mode
1 = enter Open
state upon power
alarm
N/A AOPN Direct Register 67
*Note: The ProSLIC device uses registers that are both directly and indirectly mapped. A “direct” register is one that is
mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28
through 31).
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