B&B Electronics 4 Channel Input Buffer Board SDAIBB Manual de usuario descargar pdf (Pagina 20)

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Functionality

• 4 lane PCI Express connectivity

• 10 channels 125 MS/s 16-bit ADC

• 10 MS/s to 125 MS/s per channel sampling speed

• XC6VLX130T-2FFG1156C Xilinx

• 100 MSample DDR3 buffer memory per channel

• AC and DC input stage

• ADC inputs through Rear Transition Module (RTM)

• internal, front panel, RTM and backplane clock sources

• two 16-bit DACs for fast feedback implementation

• Front panel or Zone 3 DAC routing

• FPGA, RTM_CLK4, DIV0 and DIV1 DAC clock sources

• high precision clock distribution circuitry

• programmable delay of dual channel digitizer groups

• Gigabit link port implementation to backplane

• 6.5 GBit/s on point to point links

• extended MGT clocking scheme

• twin SFP card cage for high speed system interconnects

• Front panel grounding block

• Zone 3 class A1.1 compliant

SIS8300-L 10 channel 16-bit 125 MS/s

MTCA.4 Digitizer

SIS8325 10 channel 16-bit 250 MS/s

MTCA.4 Digitizer

SIS8300-L MTCA.4 Digitizer

The SIS8300-L is a Xilinx Virtex 6 based complement to the

SIS8300. It is targeted to applictions with more demanding

link speed- and FPGA resource requirements.

Enhancements related to clocking and a change in the memo-

ry architecture were implemented while the basic architecture

and functionality of the SIS8300 were preserved.

Note: A SIS8300-L version without front

panel SMA and Harlink connectors is availa-

ble also.

The SIS8325 design doubles the maximum sampling speed

of the SIS8300-L. Texas Instruments latest ADS42LB69

digitizer chip is used on the card.

The development is done in a co-operation with DESY in the

Helmholtz Validation Funds (HVF) framework.

Functionality

• 4 lane PCI Express connectivity

• 10 channels 250 MS/s 16-bit ADC

• 250 MS/s per channel sampling speed

• XC6VLX130T-2FFG1156C Xilinx

• other parameters like SIS8300-L

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